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rev. 0.6 9/10 copyright ? 2010 by silicon laboratories si4311 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si4311 315/433.92 mh z fsk r eceiver features applications description the si4311 is a fully-integrated fsk cmos rf receiver that operates in the unlicensed 315 and 433.92 mhz ultra high frequency (uhf) bands. it is designed for high-volume, cost-sensitive rf rece iver applications, such as set-top box rf receivers, remote controls, garage door openers, home automation, security, remote keyless entry system s, wireless pos, and tele metry. the si4311 offers industry-leading rf performance, high in tegration, flexibility, low bom, small board area, and ease of design. no production alignment is necessary as all rf functions are integrated into the device. functional block diagram ? single chip receiver with only six external components ? selectable 315/433.92 mhz carrier frequency ? supports fsk modulation ? high sensitivity (?104 dbm @ 5 kbps) ? excellent interference rejection ? selectable if bandwidths ? automatic frequency centering (afc) ? data rates up to 10 kbps ? direct battery operation with on- chip low drop out (ldo) voltage regulator ? 16 mhz crystal oscillator support ? 3x3x0.85 mm 20l qfn package (rohs compliant) ? ?40 to +85 c temperature range ? satellite set-top box receivers ? remote controls, ir replacement/extension ? garage and gate door openers ? home automation and security ? remote keyless entry ? after market alarms ? te l e m e t r y ? wireless point of sale ? to y s si4311 rx_in agc antenna ldo vdd gnd 2.7 ? 3.6 v lna xtal osc rst afc adc adc pga dsp mcu baseband processor squelch 16 mhz afc 315/434 dev[1:0] dout bt[1:0] patents pending ordering information: see page 14. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 nc xtl2 bt0 bt1 dout gnd afc vdd rst xtl1 vdd vdd rfgnd rx_in dev0 nc nc dev1 gnd 315/434 si4311 (top view)
si4311 2 rev. 0.6
si4311 rev. 0.6 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. typical application bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. receiver description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. carrier frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. bit time bt[1:0] selectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5. frequency deviation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. automatic frequency centering (afc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7. low noise amplifier input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8. crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9. reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. pin descriptions: si4311- b11-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1. si4311 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. package outline: si4311- b11-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. pcb land pattern: si4311-b11- gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
si4311 4 rev. 0.6 1. electrical specifications table 1. recommended operating conditions* parameter symbol test condition min typ max unit supply voltage v dd 2.7 3.3 3.6 v supply voltage powerup rise time v dd-rise 10 ? ? s ambient temperature t a ?40 25 85 c *note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 ? c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v dd + 0.3) v operating temperature t op ?45 to 95 ? c storage temperature t stg ?55 to 150 ? c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data shee t. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si4311 device is a high-performance rf integrated circuit with certain pins ha ving an esd rating of < 2 kv hbm. handling and assembly of this device should only be done at esd-protected workstations. 3. for input pins 315/434, afc, bt[1:0], and dev[1:0]. 4. at rf input pin rx_in.
si4311 rev. 0.6 5 figure 1. reset timing table 3. dc characteristics (t a = 25 c, v dd = 3.3 v, r s = 50 ? , f rf = 433.92 mhz unless otherwise noted) parameter symbol test condition min typ max unit supply current i vdd ?20?ma reset supply current i rst reset asserted ? 2 tbd a high level input voltage 1 v ih 0.7 x v dd ?v dd +0.3 v low level input voltage 1 v il ?0.3 ? 0.3 x v dd v high level input current 1 i ih v in =v dd =3.6v ?10 ? 10 a low level input current 1 i il v in =0v, v dd =3.6v ?10 ? 10 a high level output voltage 2 v oh i out = 500 a 0.8 x v dd ??v low level output voltage 2 v ol i out = ?500 a ? ? 0.2 x v dd v notes: 1. for input pins 315/434, afc, bt[1:0], and dev[1:0]. 2. for output pin dout. table 4. reset timing characteristics (v dd =3.3v, t a =25c) parameter symbol min typ max unit rst pulse width t srst 100 ? ? s 70% 30% t srst rst
si4311 6 rev. 0.6 table 5. si4311 receiver characteristics (t a =25c, v dd =3.3v, r s =50 ? , f rf = 433.92 mhz unless otherwise noted) parameter symbol test condition min typ max unit sensitivity @ ber = 10 -3 (note 1) 1.0 kbps, ? f = 50 khz, xtal = 20 ppm, 315 mhz (note 2) ? ?104 ? dbm 10 kbps, ? f = 50 khz, xtal = 20 ppm, 315 mhz (note 2) ? ?101 ? dbm 1.0 kbps, ? f = 50 khz, xtal = 20 ppm, 433.92 mhz (note 2) ? ?102 ? dbm 10 kbps, ? f = 50 khz, xtal = 20 ppm, 433.92 mhz tbd ?100 ? dbm data rate 3 ? ? 10 kbps adjacent channel rejection 200 khz 1 desired signal is 3 db above sensitivity (ber = 10 ?3 ), unmodulated interferer is at 200 khz, rejection measured as difference between desired signal and interferer level in db when ber = 10 ?3 tbd 35 ? db alternate channel rejection 400 khz 1,2 desired signal is 3 db above sensitivity (ber = 10 ?3 ), unmodulated interferer is at 400 khz, rejection measured as difference between desired signal and interferer level in db when ber = 10 ?3 ? 55 ? db image rejection, if = 128 khz 1,2 ? 35 ? db blocking 1,2 2 mhz, 2.4 kbps, desired signal is 3 db above sensitivity, cw interferer level is increased until ber = 10 ?3 ? 65 ? db 10 mhz, 2.4 kbps, desired signal is 3 db above sensitivity, cw interferer level is increased until ber = 10 ?3 ? 70 ? db maximum rf input power 1,2 ? 8 ? dbm input ip3 3 | f 2 ?f 1 | = 5 mhz, high gain mode, desired signal is 3 db above sensitivity, cw interference levels are increased until ber = 10 ?3 ??10?dbm fsk deviation input range 3 10 ? 90 khz lna input capacitance 3 ? 7 ? pf rx boot time 3 from reset ? 320 ? ms notes: 1. 1.0 kbps, ? f = 50 khz, xtal = 20 ppm, afc = 0, bt[1:0] = 00, dev[1:0] = 01. 2. guaranteed by characterization. 3. guaranteed by design.
si4311 rev. 0.6 7 table 6. crystal characteristics (v dd = 3.3 v, t a =25c) parameter symbol test condition min typ max unit crystal oscillator frequency ? 16 ? mhz crystal esr ? ? 100 ? xtl1, xtl2 input capacitance ? 11 ? pf
si4311 8 rev. 0.6 2. typical application schematic figure 2. si4311 fsk 433.92 mhz application schematic 2.1. typical applicat ion bill of materials table 7. si4311 typical application bill of materials component(s) value/description supplier(s) c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c2 time constant capacitor, 1 f murata c3 antenna matching capacitor, 15 pf murata l1 antenna matching inductor, 33 nh for 433.92 mhz and 62 nh for 315 mhz murata r1 time constant resistor, 20 k ? murata x1 16 mhz crystal hosonic u1 si4311 315/433.92 mhz fsk receiver silicon laboratories u1 si4311-gm 20 19 18 17 16 vdd rfgnd rx_in rst afc bt0 bt1 dout gnd vdd nc nc nc dev0 dev1 434 gnd vdd xtl1 xtl2 1 2 3 4 5 15 14 13 12 11 vbattery 2.7 to 3.6 v 6 7 8 9 10 rx antenna c1 22 nf x1 (16 mhz) r1 20 k dout dev1 bt0 bt1 vdd vdd l1 gnd pad c3 c2 1 uf afc dev0
si4311 rev. 0.6 9 3. functional description 3.1. overview figure 3. functional block diagram the si4311 is a fully-integrated fsk cmos rf receiver that operates in the unlicensed 315 and 433.92 mhz ultra high frequency (uhf) bands. it is designed for high-volume, cost-sensitive rf receiver applications. the chip operates at a carrier frequency of 315 or 433.92 mhz and supports fsk digital modulation with data rates of up to 10 kbps. the device leverages silicon labs? patented and proven digital low-if architecture an d offers superior sensitivity and interference rejection. the si4311 can achieve superior sensitivity in the presence of large interference due to its high dynamic range adcs and digital filters. the digital low-if architecture also enables superior blocking ability and low inte rmodulation distortion for robust reception in the presence of wide-band interference. digital integration reduces the number of required external components compared to traditional offerings, resulting in a solution that only requires a 16 mhz crystal and passive components allowing a small and compact printed circuit board (pcb) implementation area. the high integration of the si4311 improves the system manufacturing reliability, improves quality, eases design-in, and minimizes costs. 3.2. receiver description the rf input signal is amplified by a low-noise amplifier (lna) and down-converts to a low intermediate frequency with a quadrature image-reject mixer. the mixer output is amplified by a programmable gain amplifier (pga), filtered , and digitized with a high- resolution analog-to-digi tal converter (adc). all rf functions are integrated into the device eliminating any production alignment issues associated with external components, such as saw and ceramic if filters. silicon labs? advanced digi tal low-if architecture achieves superior perfo rmance by using the dsp to perform channel filtering, demodulation, automatic gain control (agc), automatic frequency control (afc), and other baseband processing. dsp implementation of the channel filters provides better repeatability and control of the bandwidth and frequency response of the filter compared to analog implementations. no off-chip ceramic filters are needed with the si4311 since all if channel filtering is performed in the digital domain. 3.3. carrier frequency selection the si4311 can be tuned to either 315 or 433.92 mhz by driving pin 6 (315/434 ) to vdd or gnd. the 315 mhz operation is chosen by driving pin 6 (315/434 ) to vdd, and 433.92 mhz operation is chosen by driving pin 6 (315/434 ) to gnd. si4311 rx_in agc antenna ldo vdd gnd 2.7 ? 3.6 v lna xtal osc rst afc adc adc pga dsp mcu baseband processor squelch 16 mhz afc 315/434 dev[1:0] dout bt[1:0]
si4311 10 rev. 0.6 3.4. bit time bt[1:0] selection the si4311 can operate with data rates of up to 10 kb ps non-return to zero (nrz) data or 5 kbps manchester encoded data. however, fsk modulation uses other enc oding schemes, such as pulse width modulation (pwm) and pulse position modulation (ppm) in which a bit can be encoded into a pulse with a certain duty cycle or pulse width (see figure 4). figure 4. example data waveforms in order to set the data filter bandwidth correctly, the shortest pulse width of the transmitted encoded data should be chosen as the bit time. in the ppm example shown in fi gure 4, the shortest pulse width is 100 s, so the bit time is chosen as bt = 100 s even though t he actual data rate is 1 kbps (1000 s). after finding bt, table 9 can be used to find the bit settings for pins 14 and 15, bt[1:0]. in this ppm example, bt[1:0] is set as logic bt1 = 1 and bt0 = 1 or bt[1:0] = (1,1) since bt = 100 s. table 8. carrier frequency selection pin 6 (315/434 )frequency [mhz] 0 433.92 1315 table 9. how to choose bt[1:0] based on the bit time bit time [us] bt1 (pin 14) bt0 (pin 15) bt 1000 0 0 1000< bt 500 0 1 500 < bt 200 1 0 200 < bt 100 1 1 nrz encoding digital data manchester encoding ppm encoding ?1? ?0? ?1? ?1? 1000 us 100 us
si4311 rev. 0.6 11 3.5. frequency d eviation selection in order to accommodate wide frequency deviation ranges, the si4311 fsk receiver uses two input pins, pins 16 and 17, to select a range of frequency deviations as s hown in table 10. for example, if the fsk signal has a frequency deviation ( ? f) of 50 khz, then the dev[1:0] = (0,1) or pin 16 = 0 and pin 17 = 1. 3.6. automatic freq uency centering (afc) the channel bandwidth directly affects the sensitivity of any wireless receiver. typica l analog fsk receivers use an external ceramic filter with a large bandwidth to accommodate the data rate, frequency deviation, crystal tolerances, and transmit carrier frequency offsets, wh ich leads to unnecessary amounts of noise and lower sensitivity levels. the si4311 uses a narrow channel bandwidth of 200 khz and autom atic frequency centering (afc) to obtain excellent sensitivity levels (?104 dbm at data rate of 5 k bps at 315 mhz) while still accommodating up to 200 khz of frequency tracking from its center frequency. figure 5. (a) ideal case (b) scenario with tx offset (c) si4311 afc re-centers if bw in the ideal case of no transmit carrier frequency errors or receiver frequency errors, both fsk tones for a logic "1" and "0" from the transmitter appear in the receiver if channel bandwidth as shown in figure 5 (a). however, if the transmitter has a large carrier offset such as shown in figure 5 (b), then only one of the fsk tones falls in the receiver channel bandwidth and thus the receiver produces errors. the standard approach to resolving this problem is to use an if channel filter that is large enough to accommodate the transmitter frequency error, but this leads to degraded sensitivity. the si4311 uses afc to re-center the channel bandwidth about the two fsk tones as shown in figure 5 (c) to maintain ex cellent sensitivity with a small if chann el filter. the algorithm requires one fsk tone to be in-band and at most three alternating se quences of 0/1 data typically found in a preamble plus 700 s of fixed delay time (approximately 230 s per 0/1 data pair) to re-center the if bandwidth. worst case acquisition time is 1.3 ms for a data rate of 10 kbps. the afc algorithm includes a 200 ms hold time. the device holds the frequency found by the afc algorithm for a time of 200 ms after no rf signal activity before rest arting the frequency search. this allows a frequency found in the first packet of transmission to be held for any subsequent retransmissions of packets if the retransmissions occur before 200 ms. this hold frequency ensures all bi ts of the second and subsequent packets are recovered completely. the afc frequency search resumes after 200 ms of no rf signal activity. the afc algorithm can be disabled by setting the logic level on pin 5 to a logic zero as shown in table 11. table 10. frequency deviation range settings dev1 (pin 16) dev0 (pin 17) frequency deviation [khz] 00 1 < ? f 30 01 30 < ? f 50 10 50 < ? f 70 11 70 < ? f 90 200khz if bw (a) tx offset 100khz (b) (c) tx offset 100khz
si4311 12 rev. 0.6 3.7. low noise amplifier input circuit figure 2 shows the typical application circuit with 50 ? matching. components c3 and l1 are used to transform the input impedance of the lna. c3 is equal to 15 pf and l1 is equal to 33 nh at 433.92 mhz and 62 nh at 315 mhz for 50 ? matching. 3.8. crystal oscillator an on-board crystal oscillator is us ed to generate a 16 mhz reference cl ock for the si4311. this reference frequency is required for proper operation of the si4311 and is used for calibration of the on-chip vco and other timing references. no external load capacitors are required to set the 16 mhz reference frequency if the recommended crystal load capacitor is around 14 pf, assuming the effective board capacitance between pins xtl1 and xtl2 is 3 pf and the chip input capacitance on pins xtl1 or xtl2 is 11 pf. refer to table 6, ?crystal characteristics,? on page 7 for board capacitance and frequency tolerance information. the frequency tolerance of the crystal should be chosen such that the received sign al is within the if bandwidth of the si4311 receiver. additionally, the si4311 can be driven by an external 16 mhz reference clock. the clock signal can be applied to either the xtl1 or xtl2 inputs. when the 16 mhz reference clock is applied to one of the inputs, the other crystal input pin must be floating. 3.9. reset pin driving the rst pin (pin 4) low will disable the si4311 and place the device into rese t mode. all active blocks in the device are powered off in this mode, bringing the curren t consumption to <10 ua. the si4311 is enabled by driving the rst pin (pin 4) to vdd. refer to table 4 "reset timing characteristics" fo r the reset timing requirements. the chip requires about 320 ms to go from reset to active mode. the si4311 can output invalid data during the 320 ms turn-on time. table 11. afc selection pin 5 pin 5 afc 0 disable 1 enable
si4311 rev. 0.6 13 4. pin descriptions: si4311-b11-gm pin number(s) name description 1, 8, 11 vdd supply voltage, may connect to external battery. 2 rfgnd rf ground. connect to ground plane on pcb. 3 rx_in rf receiver input. 4rst device reset, active low input. 5 afc afc selection input pin. 6 315/434 selectable logic input for 315 or 433.92 mhz operation. 7, 12, gnd pad gnd ground. connect to ground plane on pcb. 9 xtl1 crystal input. 10 xtl2 crystal input. 13 dout data output. 14, 15 bt[1:0] bit time selection input pins. 16,17 dev[1:0] frequency deviation input pins. 18,19,20 nc no connect. leave floating. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 nc xtl2 bt0 bt1 dout gnd afc vdd rst xtl1 vdd vdd rfgnd rx_in dev0 nc nc dev1 gnd 315/434
si4311 14 rev. 0.6 5. ordering guide part number* description package type operating temperature si4311-b11-gm 315/433.92 mhz fsk receiver qfn pb-free ?40 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option.
si4311 rev. 0.6 15 6. package markings (top marks) 6.1. si4311 top mark figure 6. si4311 top mark example 6.2. top mark explanation mark method: yag laser line 1 marking: part number 11 = si4311 firmware revision 11 = firmware revision 1.1 line 2 marking: die revision b = revision b die ttt = internal code internal tracking code line 3 marking: circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier yww = date code assigned by the assembly house. corresponds to the last digit of the current year (y) and the workweek (ww) of the mold date.
si4311 16 rev. 0.6 7. package outline: si4311-b11-gm figure 7 illustrates the package details for the si4311-b11-gm. table 12 lis ts the values for the dimensions shown in the illustration. figure 7. 20-pin quad flat no-lead (qfn) table 12. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 f 2.53 bsc a1 0.00 0.02 0.05 l 0.30 0.35 0.40 b 0.20 0.25 0.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si4311 rev. 0.6 17 8. pcb land pattern: si4311-b11-gm figure 8 illustrates the pcb land pattern details for th e si4311-b11-gm. table 13 lists the values for the dimensions shown in the illustration. figure 8. pcb land pattern
si4311 18 rev. 0.6 table 13. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder-mask -defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4311 rev. 0.6 19 d ocument c hange l ist revision 0.1 to revision 0.2 ? maximum data rate changed from 10 to 4 kbps for fsk and from 5 to 2 kbps for ook with manchester encoding. ? maximum rf input power changed from 5 to 10 dbm. ? changed test conditi ons for sensitivity measurements and added the xtal frequency tolerance of 20 ppm. ? updated text in section ?3 . functional description?. ? added ideal if bandwidth equation and description for choosing the if bandwid th in section ?3.4. bit time bt[1:0] selection?. ? updated table 11, ?typical sensitivity @ 433 mhz, 2-fsk,? on page 11. ? changed hysteresis level from 1 db to 6 db in section ?3.8. crystal oscillator?. ? added text in section ?3 .8. crystal oscillator? regarding the crystal frequency tolerance and if bandwidth choice and sensitivity performance. revision 0.2 to revision 0.3 ? updated features list ? reduced font size in the test condition section of table 5 "si4311 receiver characteristics" ? added crystal tolerance equation to table 6 "crystal characteristics" ? updated matching circuit and bom to section ?2. test circuit? and section ?2. typical application schematic? ? modified text in section ?3. functional description? ? changed bandwidth option in table 11 "bandwidth selection table using bw[3:1] pins" and test mode. ? reset section updated to reflect active blocks are powered off in reset mode. revision 0.3 to revision 0.4 ? removed crystal frequency tolerance range from table 6 "crystal characteristics". ? corrected data rates in section ?3.1. overview?. ? updated text in section ?3.4. bit time bt[1:0] selection? to show f sk receive if bandwidth equations. ? deleted voltage gain text in section ?3.7. low noise amplifier input circuit?. ? removed squelch circuit description in section ?3.8. crystal oscillator?. ? included load capacitance requirement for crystal if no external capacitors are used in section ?3.8. crystal oscillator?. ? added reset to active time in section ?3.9. reset pin?. ? changed ordering guide part number in section ?5. ordering guide?. ? added fsk automatic frequency calibration information ? removed ook feature. revision 0.4 to revision 0.5 ? removed i vdd current spec when input = ?30 dbm from table 3 "dc characteristics" ? updated sensitivity specs and test conditions in table 5 "si4311 receiver characteristics" ? added afc hold time description to section ?3.6. automatic frequency centering (afc)? ? added reference clock driv e capability to section ?3.8. crystal oscillator? revision 0.5 to revision 0.6 ? updated part number to si4311-b11-gm
si4311 20 rev. 0.6 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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